Efficient manufacture of submicron very large scale integration (VLSI) circuits includes the need for increased packing density, reduced device parasitics, low resistivity interconnects and high resolution lithography. Various buried contact and self-aligned contact schemes have been developed to increase the number of devices per unit area, avoid the necessity of defining small contacts and relax alignment tolerances. Silicides have been increasingly used to reduce device parasitic resistances as well as interconnect resistances.
Polycrystalline silicon (poly) gates conventionally have been connected to source and drain regions through the use of metal. Metal has many design limitations including interlevel oxide formation and capacitance concerns. Metal is difficult to deposit and etch, resulting in the large allowances required for possible misalignment. Because metal is hard to process into useful contacts, the prior art has suggested reducing the design rule pressure on the metal by adding a second metal level. The problem with this suggested solution is that this secondary metal is even more sensitive to design rule constraints. Metal, therefore, is a limiting factor. Local interconnect (LI) was invented to connect certain poly gates to certain active semiconductor regions without using metal one in the contact to the poly.
Titanium silicide technology implemented in local interconnects (LI) is of particular interest for application in fast logic circuits and also benefits the full complementary metal-oxide semiconductor (CMOS) static random access memory (SRAM), since substrate and well contacts can be made to every cell without sacrificing area. Titanium silicide has been proposed to be used as LI material in self-aligned titanium silicide technology. See Philips, A 1M SRAM With Full CMOS Cells Fabricated In A 0.7 .mu.M Technology (1987); Hewlett Packard, A New Device Interconnect Scheme For Sub-Micron VLSI (1984). The titanium silicide LI provides the flexibility to extend the junction area for self-registered contacts to further increase packing density. As published in the literature, this titanium silicide LI process includes successive depositions of titanium and amorphous silicon (a-Si), an LI pattern and an amorphous silicon etch, a titanium silicide reaction and an anneal. However, due to rapid dopant outdiffusion and, more importantly, the differential titanium silicide formation on single crystal Si, poly-Si and amorphous silicon, this technology can be used only with some additional design rule constraints such as between n+poly-to-p+junction which are connected by LI to preserve gate oxide integrity (GOI) and junction integrity. The rapid dopant outdiffusion through TiSi.sub.2, places limits on certain processing windows, such as thermal steps. Accordingly, such design rule constraints limit the usefulness of this process in high density VLSI circuits because a greater distance between LI connecting points means that the manufacture requires greater area. It has therefore become desirable to devise an improved titanium silicide LI process which can be fabricated without sacrificing area and which provides a longer window of processing time than those presently existing in the art.